FIG. 1 illustrates a memory plane MEM of the SRAM (Static Random Access Memory) type. The memory plane MEM conventionally includes word lines WLi and columns COLj, which each include two bit lines BLT and BLF.
The memory cells of such a memory plane, illustrated in detail in FIG. 2, are connected differentially between two bit lines BLT and BLF of each column of the memory plane and can be activated by a word line WLi. Moreover, read amplifiers SA are disposed at the foot of the columns of the memory plane and are conventionally activated by an activation signal delivered by a control circuit MC.
A memory cell of the memory plane is shown in FIG. 2. The memory cell has a first inverter gate IA and a second inverter gate IB connected in opposite orientations between a first node A and a second node B. A first access transistor TA is provided, with its drain connected to the node A, its gate connected to a word line WL of the memory plane, and its source connected to a first bit line BLT. A second access transistor TB is also provided, with its drain connected to the node B, its gate connected to the word line WL, and its source connected to the second bit line BLF of the column of the memory cell.
FIG. 3 depicts N+1 of such memory cells P0-PN, associated so as to form a column of the SRAM memory, at the foot of which a differential read amplifier SA is provided. All the memory cells P0-PN are connected to the same bit lines BLT and BLF. On the other hand, each memory cell is connected to a different word line WL0-WLN. The amplifier SA has two differential inputs connected respectively to the first bit line BLT and the second bit line BLF.
To program a memory cell in the column of memory cells, a potential Vdd is applied to the word line WL associated with the cell to be programmed and, according to the data item 0 or 1 to be programmed in the cell selected, a zero potential (connection to ground) or the potential Vdd is applied to the first bit line BLT, and a potential that is the inverse of the potential applied to the first bit line BLT is applied to the second bit line BLF. For example, in order to program a logic 0 in the memory cell P0, Vdd is applied to the word line WL0, as well as to the second bit line BLF, and the first bit line BLT is connected to ground. Thus, after the programming of a 0, the node A0 is at zero potential and the node B0 is at the potential Vdd.
During an operation for reading this memory cell P0, the two lines BLT and BLF are first precharged to the supply potential Vdd, and the corresponding word line WL0 is subjected to the potential Vdd (WL0=logic 1) in order to select the memory cell P0 in read mode (with the other word lines being connected to ground: WL1-WLN=logic 0). Then the two bit lines BLT and BLF are made to float. With the word line WL0 at the high potential Vdd, the access transistors TA0 and TB0 of the cell are on. In addition, according to this example, as the node A0 of the cell P0 is at 0 and the first line BLT is at the potential Vdd, the two sides of the channel of the transistor TAO are at different potentials so a current Iread flows through this channel. This current Iread will discharge the first bit line BLT and thus progressively return its potential to 0. On the other hand, as the node B0 of the memory cell and the second bit line BLF are at the same potential Vdd, the two sides of the channel of the transistor TB0 are at the same potential and no current flows in this channel. The second bit line BLF is therefore assumed to remain at its high precharge state (that is, at the potential Vdd).
After a certain length of time, the amplifier SA detects a difference in potential between the bit lines BLT and BLF, which, when it is greater than the input offset voltage of the amplifier, produces at the output of the amplifier a data signal corresponding to the data item stored in the selected memory cell.
Reading is thus possible only if a difference in potential of sufficient amplitude (greater than the offset voltage of the amplifier) appears between the bit lines BLT and BLF.
So that the amplifier can correctly detect the difference in potential expected between the two bit lines BLT and BLF and thus obtain the correct read value, it is therefore essential for the amplifier to be activated at the correct time, that is when the difference in potential between the two bit lines, the one discharging and the one assumed to remain at its high precharged state, is greater than the offset voltage of the amplifier.
However, a phenomenon of leakage currents inherent in the access transistors of the memory cells in the column complicates the control of the activation of the read amplifier. More precisely, because of stray leakage currents in the memory cells of the column being read, the second bit line BLF that is assumed to remain at its high precharged state is in reality also drawn toward ground.
This is because, even when correctly blocked by an appropriate potential applied to its gate, a transistor has leak current when a difference in potential appears between its drain and source. In the example in FIG. 3, with the memory cell P0 storing a logic 0, it is assumed that the other memory cells P1-PN store the inverse data item, namely a logic 1. The nodes A1-AN are thus at 1 and the nodes B1-BN are at 0. With the memory cell P0 being selected in read mode (WL0=1), although the access transistors TB1-TBN are off (WL1-WLN=0), leakage currents Ioff are nevertheless established between the drain and the source of the transistors TB1-TBN, related to the difference in potential between the second bit line BLF precharged to the high state and the nodes B1-BN at 0. These leakage currents Ioff will together progressively discharge the potential of the bit line BLF, which was assumed to remain at its high precharged state and, consequently, reduce the signal applied to the input of the read amplifier.
Normally, the memory is equipped with a reference path (“dummy path”) CHdum (FIG. 1) that is intended to automatically adjust the time of delivery by the control circuit MC of the activation signal that activates the read amplifiers disposed at the foot of the columns of the memory plane.
This dummy path includes a dummy column, formed by two dummy bit lines DBLT and DBLF. Dummy memory cells CELDi are connected to this dummy column, and at least one of them CELD1 is activated by a dummy word line DWL.
The dummy memory cell CELD1 activated by the dummy word line DWL is programmed so as to discharge (to draw toward ground) one of the dummy bit lines, with the other having the leakage current pass through it. The dummy bit line that is intended to be discharged when the dummy cell CELD1 is activated is then used, in a known manner, to generate the activation signal Act for activating the read amplifiers of the memory plane through the control circuit MC. For example, the dummy bit line intended to be discharged when the dummy cell is activated is connected to the input of an inverter gate provided within the control circuit MC to deliver the activation signal Act.
In practice, several dummy memory cells CELD1-CELDn are in fact activated by the word line DWL so as to produce a discharge of the dummy bit line that is more rapid than the discharge of a standard bit line BLT of a column in the memory plane.
Moreover, in order to compensate for the effects of the leakage currents mentioned above and to obtain a memory that functions in a high temperature range in particular, a delay circuit is generally inserted in the dummy path, in order to delay the delivery of the activation signal for activating the read amplifiers so as to obtain a correct functioning of the memory in a worst case situation (for example, when there is a high temperature for which the leakage currents are high).
However, such a solution, though it leads to acceptable performance in the worst case situation, degrades the performance of the memory in the intermediate and normal operating situations.
Another solution is to actually take into account the leakage current of the bit line that is not supposed to discharge in the activation of the read amplifiers, at each column of the memory plane. Such a solution consists of, during an operation for reading a memory cell, first evaluating the leakage current of each of the bit lines in order to then be able to re-inject this leakage current of each of the two bit lines into the other, so that the effect of the leakage currents in each of the two bit lines thus compensate for each other mutually.
This solution is however expensive, in particular in terms of size occupied by the memory, because it involves providing specific circuitry at each of the columns of the memory plane, both to evaluate the leakage currents and to re-inject these leakage currents into the bit lines during the reading operation.
In addition, the phase of evaluating the leakage current on the bit line that is not supposed to discharge, having to be implemented prior to any read phase itself, is detrimental in terms of the operating speed of the memory.